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Asymmetrical multilevel inverter topology with reduced number of components
conference contribution
posted on 2018-01-01, 00:00 authored by M D Siddique, S Mekhilef, N M Shah, A Sarwar, M A Memon, Mohammadmehdi Seyedmahmoudian, Ben HoranBen Horan, Aleksandar Stojcevski, K Ogura, M Rawa, H BassiA new hybrid structure of multilevel inverter topology is recommended in this paper. It is designed with the aim of reducing the number of components with more number of levels at the output. Proposed topology uses three dc voltage sources along with 10 power semiconductor devices to achieve 13 levels at the output. A comparative study is given with other similar topologies which proves the lower number of components. In order to achieve good-quality output voltage, selective harmonic elimination technique is used with the elimination of lower order harmonics. Different simulation results have been provided to validate the proposed topology.
History
Event
IEEE Industry Applications Society. Conference (2018 : Chennai, India)Series
IEEE Industry Applications Society ConferencePagination
1 - 5Publisher
Institute of Electrical and Electronics EngineersLocation
Chennai, IndiaPlace of publication
Piscataway, N.J.Publisher DOI
Start date
2018-12-18End date
2018-12-21ISBN-13
9781538693155Language
engPublication classification
E1 Full written paper - refereedCopyright notice
2018, IEEEEditor/Contributor(s)
[Unknown]Title of proceedings
PEDES 2018 : Proceedings of the 2018 IEEE International Conference on Power Electronics, Drives and Energy SystemsUsage metrics
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