Deakin University
Browse

File(s) under permanent embargo

Single phase symmetrical and asymmetrical design of multilevel inverter topology with reduced number of switches

conference contribution
posted on 2018-06-13, 00:00 authored by M D Siddique, A Mustafa, A Sarwar, S Mekhilef, N B M Shah, M Seyedamahmousian, A Stojcevski, Ben HoranBen Horan, K Ogura
© 2018 IEEE. Multilevel Inverters have shaped a new trend of importance in industry and research. A new topology of multilevel inverter is proposed in this paper which can be operated in symmetrical and asymmetrical modes. The proposed topology produces 7-level and 13-level staircase output voltage waveform for symmetrical and asymmetrical configuration respectively using only 10 switches. The gate signals for the different switches are produced employing the fundamental frequency switching technique. The topology achieves better performance using a lower minimum number of components in comparison to conventional inverters. These improvements result in reduced system cost and size. Simulations are carried out using MATLAB/SIMULINK environment and experimental implementation using laboratory prototype module have ascertained the performance and operation of the proposed topology.

History

Event

IEEMA Engineer Infinite. Conference (2018 : Greater Noida, Uttar Pradesh)

Pagination

1 - 6

Publisher

IEEE

Location

Greater Noida, Uttar Pradesh

Place of publication

Piscataway, N.J.

Start date

2018-03-13

End date

2018-03-14

ISBN-13

9781538611388

Language

eng

Publication classification

E Conference publication; E1 Full written paper - refereed

Title of proceedings

eTechNxT 2018 : Proceedings of the IEEMA Engineer Infinite Conference,

Usage metrics

    Research Publications

    Categories

    No categories selected

    Exports

    RefWorks
    BibTeX
    Ref. manager
    Endnote
    DataCite
    NLM
    DC